What You’ll Be Doing

Apply formal verification techniques to various design parts.
Review functional and micro-architectural specifications to define formal verification scopes.
Develop high-quality formal verification test plans for design implementation sign-off.
Create formal verification testbenches, code assertions, constraints, and abstraction techniques.
Use formal coverage techniques to analyze over-constraints and measure functional coverage.
Collaborate with the Synopsys Tool Development Group to drive verification projects.

Required Skills
Verilog, SystemVerilog, SystemVerilog Assertions (SVA), Hardware Micro-architecture, Formal Property Verification, Python, Perl, Shell Scripting, Debugging, Problem-solving

Who You Are

Excellent communicator with strong interpersonal skills.
Team player thriving in collaborative environments.
Detail-oriented with strong analytical and problem-solving skills.
Proactive learner staying updated with industry trends.
Passionate and motivated professional with a keen interest in technology.

What You’ll Gain

Hands-on experience in formal verification projects.
Collaboration with a dynamic and innovative team.
Opportunity to contribute to high-quality IP development.
Exposure to industry-leading verification methodologies and tools.

Rewards and Benefits
Synopsys offers a comprehensive range of health, wellness, and financial benefits to cater to your needs. Your recruiter will provide details about the salary range and benefits during the hiring process.

Inclusion and Diversity
We value diversity and consider all applicants regardless of race, color, religion, national origin, gender, sexual orientation, gender identity, age, veteran status, or disability.

Apply Now
Be a part of a team that values collaboration, creativity, and excellence, and is committed to pushing the boundaries of technology.

Education Requirement: Pursuing or completed BTech/MTech in Electrical Engineering, Computer Engineering, or a related field

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